Semiconductor devices dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to connect the die to higher level circuitry.
Forming the semiconductor devices can include forming a substrate 102 with traces 104 exposed thereon. As illustrated in FIG. 1, the traces 104 can be exposed based on removing solder mask 106 in solder mask opening area, thereby also exposing a top surface of the substrate top and peripheral surfaces of traces 104.
As further illustrated in FIG. 1, a separately assembled structure, which includes a die 110 with pillars 112 and wafer-level underfill 130 encapsulating the pillars 112 and a surface on the die 110, can be aligned and attached to the substrate 102 and the traces 104. The attachment process can include reforming or reflowing the wafer-level underfill 130 (e.g., such as by controlling the temperature thereof to change its viscosity level), which travels downward as illustrated in FIG. 1 to fill a space between the die 110 and the substrate 102.
As further illustrated in FIG. 2, a resulting semiconductor device 202 (e.g., after reflowing the wafer-level underfill 130 and curing the wafer-level underfill 130 to form an encapsulant) can include the wafer-level underfill 130 filling a space between the die 110 and the substrate 102. The wafer-level underfill 130 can further encapsulate the traces 104. However, due to various factors (e.g., viscosity level of the wafer-level underfill 130, trapped air/gases, uneven flow of the wafer-level underfill 130, space between the traces, etc.), the reflowing process can leave voids 204 directly adjacent to some of the traces 104 (e.g., with portions of the traces 104 failing to directly contact the wafer-level underfill 130). The voids 204 between the traces 104 can cause shorting and leakage between the traces 104, causing an electrical failure for the semiconductor device 202.